Low Power Design / Verification Engineer (UPF)
- Experis
- 4 - 9 years
- Hyderabad
- 21 days ago
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Job Description
Hi, Greetings from Experis IT! We are happy to shortlist your candidature for an interview with one of our leading IT clients eInfochips. Please find the details below: Position: Low Power Design / Verification Engineer (UPF)Company: eInfochipsJob Type: Permanent Location: Bangalore / Hyderabad / Noida / PuneExperience: 4+ Years
Job Description:We are seeking a skilled Low Power Design / Verification Engineer with strong expertise in Unified Power Format (UPF) and low-power design methodologies. The candidate will be responsible for implementing and verifying low-power architectures to optimize power consumption in advanced SoC designs.
Key Responsibilities:
- Implement and verify low-power design techniques using UPF (Unified Power Format).
- Develop and maintain power intent specifications and integrate them into RTL design and verification environments.
- Perform low-power verification including power-aware simulation and debugging.
- Collaborate with design, verification, and physical design teams to ensure proper power domain implementation.
- Validate power management strategies such as power gating, clock gating, retention, and isolation.
- Debug low-power issues across RTL, gate-level simulations, and power-aware verification environments.
- Ensure compliance with low-power design methodologies and best practices.
Required Skills:
- Strong knowledge or hands-on experience with UPF (Unified Power Format).
- Experience in low-power verification/design methodologies.
- Understanding of power domains, isolation cells, retention registers, and power gating.
- Experience with power-aware simulation tools and verification environments.
- Knowledge of RTL design (Verilog/SystemVerilog).
- Familiarity with SoC architecture and low-power implementation techniques.
Preferred Qualifications:
- Experience with industry tools such as Cadence, Synopsys, or Siemens EDA tools for low-power verification.
- Experience in ASIC/SoC design and verification flows.
- Exposure to advanced low-power optimization techniques.
Education:
- Bachelors or Masters degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
Job Classification
Industry: IT Services & ConsultingFunctional Area / Department: Engineering - Software & QARole Category: Software DevelopmentRole: Software Development - OtherEmployement Type: Full timeContact Details:
Company: ExperisLocation(s): Hyderabad
Keyskills: UPF Power Gating Low Power Design Isolation Cells Unified Power Format SoC Power Domains RTL Retention Registers SystemVerilog ASIC Verilog Clock Gating
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